Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

A circuit-level SPICE modeling strategy for the simulation of behavioral variability in ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The intrinsic behavioral variability in resistive switching devices (also known as 'memristors' or 'ReRAM devices') can be a reliability limiting factor or an opportunity for applications where randomness of resistance switching is essential, such as hardware security and stochastic computing. The realistic assessment of ReRAM-based circuits & systems towards practical exploitation requires variability-aware ReRAM modeling. In this context, here we present a versatile, circuit-level implementation strategy to incorporate cycle-to-cycle (C2C) variability to the ReRAM model parameters in SPICE simulations. We evaluated the proposed approach with threshold-based models of a voltage-controlled bipolar ReRAM device and managed to reproduce the main features observed in experimental curves for different pulsed voltage inputs. With key upgrades, compared to previous approaches found in the literature, our strategy enables the enhancement of any ReRAM device model towards the exploration of new ways to make the most of the C2C ReRAM variability, and to test the robustness of any designed circuits & systems against ReRAM variability.Supported by the Chilean research grants ANID-Basal FB0008 and FONDECYT Regular 1221747, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft

Alternative memristor-based interconnect topologies for fast adaptive synchronization of chaotic circuits

© 2020 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching devices (memristors) constitute an emerging device technology promising for a vari- ety of applications that are currently being studied. In this context, the use of memristors as coupling el- ements of the dynamics of chaotic circuits for adaptive synchronization purposes, was recently proposed and the passive crossbar array was evaluated as target interconnect medium. Nonetheless, memristors may suffer from defects and degradation. Therefore, this work evaluates the impact of memristor switch- ing faults in an adaptive chaotic synchronization scheme, exploring at the same time the fault-tolerance of the crossbar architecture. Moreover, inspired from our observations in the stuck-at-OFF fault analy- sis of the memristive crossbar, some alternative scalable memristive interconnect patterns are suggested, whose performance is found independent of the number of interconnected chaotic circuits, requiring a much smaller number of total memristors than the crossbar array. All simulations are based on an ac- curate physics-based model of a bipolar memristor with filamentary switching mechanism. Based on our results, using the alternative topologies instead of the crossbar array leads to significant savings in the synchronization time that increase with the number of interconnected chaotic units, at the cost of more limited scaling capability and fault-tolerance.This work was supported in part by the Chilean research Grants ANID REDES ETAPA INICIAL 2017 No. REDI170604, ANID FONDECYT INICIACION 11180706, ANID BASAL FB0008, and by the Spanish MINECO and ERDF under Grant TEC2016-75151-C3-2-R.Peer ReviewedPostprint (author's final draft

Circuit topology and synthesis flow co-design for the development of computational ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for in-memory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristor-oriented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells.Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33Peer ReviewedPostprint (author's final draft

Shortest path computing in directed graphs with weighted edges mapped on random networks of memristors

Electronic version of an article published as [Fernandez, Carlos, Ioannis Vourkas, and Antonio Rubio. "Shortest Path Computing in Directed Graphs with Weighted Edges Mapped on Random Networks of Memristors." Parallel Processing Letters 30.01 (2020): 2050002] [https://doi.org/10.1142/S0129626420500024] © [copyright World Scientific Publishing Company] [https://www.worldscientific.com/worldscinet/ppl]To accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the solution of complex optimization problems. Lately, the solution of the shortest-path problem (SPP) in a two-dimensional memristive grid has been given wide consideration. Some still open problems in such computing approach concern the time required for the grid to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology was extended to support weighted directed graphs. We tried memristor device models with fundamentally different switching behavior to check their suitability for such applications and the impact on the timely detection of the solution. Furthermore, the requirement of binary vs. analog operation of memristors was evaluated. Finally, the memristor network-based computing approach was compared to known algorithmic solutions to the SPP over a large set of random graphs of different sizes and topologies. Our results contribute to the proper development of bio-inspired memristor network-based SPP solvers.This work was supported by the Chilean research grants CONICYT REDES ETAPA INICIAL Convocatoria 2017 No. REDI170604, CONICYT BASAL FB0008, and by the Spanish MINECO and ERDF (TEC2016-75151-C3-2-R).Peer ReviewedPostprint (author's final draft

Effective current-driven memory operations for low-power ReRAM applications

© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Al document ha d’aparèixer l’enllaç a la publicació original a IEEE, o bé al Digital Object Identifier (DOI).Resistive switching (RS) devices are electronic components which exhibit a resistive state that can be adjusted to different nonvolatile levels via electrical stressing, fueling the development of future resistive memories (ReRAM) and enabling innovative solutions for several applications. Most works so far have used voltage-based driving schemes for both WRITE and READ operations. However, results from current-driven WRITE operations have shown high uniformity in switching performance, and thus constitute a valid alternative to consider, but current-driven READ operations have rarely been explored. In this context, here we tested a current-based READ/WRITE memory driving scheme on commercial self-directed channel (SDC) devices, while operating constantly at low current levels between tenths of nA and 1.5 uA. We propose a novel method to carry out efficient READ operations exploiting the transient response of the voltage on the current-driven ReRAM memory cells. For READ operations performed at 100 nA, we calculated the cumulative probability distribution of the standard deviation of the measured voltage ( σV ) on the devices and we observed a ratio σV−HRS/σV−LRS∼10× . Moreover, the HRS and LRS states were distinguishable in all the tested devices with less than 0.5% error. Finally, the calculated energy consumption ( ESET≈10 nJ, ERESET≈30 nJ, and EREAD between 80–400 pJ) was competitive even when the duration of the READ/WRITE current pulses was suboptimal in the millisecond range. Therefore, the presented results validate the promising characteristics and the power-efficiency of the proposed READ method for current-driven ReRAM circuits and applications.This work was supported in part by the Chilean Government through the National Fund for Scientific and Technological Development (FONDECYT) under Grant 1221747; in part by the National Agency for Research and Development (ANID)-Basal under Grant FB0008; in part by the MICINN, Spain, through PRITES Project under Grant PID2019-105658RB-I00; and in part by FLEXRRAM Project under Grant TED2021-129643B-I00.Peer ReviewedPostprint (published version

Experience on material implication computing with an electromechanical memristor emulator

Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that emulates the fundamental behavior of a memristor based on an electro- mechanical organization. By using this emulator, results about the experimental implementation of an unconventional material implication-based data-path equivalent to the i-4004 are presented and experimentally demonstrated. The use of the proposed quasi-ideal device allows the evaluation of this new computing paradigm, based on the resistance domain, without incorporating the disturbance of process and cycle to cycle variabilities observed in real nowadays devices that cause a limit in yield and behavior.Peer ReviewedPostprint (published version

Crossbar-based memristive logic-in-memory architecture

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.Peer ReviewedPostprint (author's final draft

Stochastic resonance exploration in current-driven ReRAM devices

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Advances in emerging resistive random-access memory (ReRAM) technology show promise for its use in future computing systems, enabling neuromorphic and memory-centric computing architectures. However, one aspect that holds back the widespread practical use of ReRAM is the behavioral variability of resistive switching devices. In this context, a radically new path towards ReRAM-based electronics concerns the exploitation of noise and the Stochastic Resonance (SR) phenomenon as a mechanism to mitigate the impact of variability. While SR has been already demonstrated in ReRAM devices and its potential impact has been analyzed for memory applications, related works have only focused on voltage input signals. In this work we present preliminary results concerning the exploration of SR in current-driven ReRAM devices, commercially available by Knowm Inc. Our results indicate that additive noise of amplitude s = 0.125uA can stabilize the cycling performance of the devices, whereas higher noise amplitude improves the HRS-LRS resistance window, thus could affect positively the Bit Error Rate (BER) metric in ReRAM memory applications.Supported by the Chilean research grants FONDECYT INICIACION 11180706 and ANID-Basal FB0008, and by the Spanish MCIN grants PID2019-105658RB-I00, and MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33.Peer ReviewedPostprint (author's final draft

An on-line test strategy and analysis for a 1T1R crossbar memory

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array.Peer ReviewedPostprint (author's final draft